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<p>
This circuit is a
<a href="http://en.wikipedia.org/wiki/Flip-flop_(electronics)#Master-slave_D_flip-flop">master-slave
D flip-flop</a>. A D flip flop takes only a single input, the D (data) input. The master-slave
configuration has the advantage of being edge-triggered, making it easier to use in larger
circuits, since the
inputs to a flip-flop often depend on the state of its output.
<p>
The circuit consists of two D flip-flops connected together. When the clock is high,
the D input is stored in the first latch, but the second latch cannot change state. When the clock
is low, the first latch's output is stored in the second latch, but the first latch cannot
change state.
<p>
The result is that output can only change state when the clock makes a transition from high to low.
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Next: <a href="e-edgedff.html">Edge-Triggered D Flip-Flop</a><p>
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