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<title>Edge-Triggered D Flip-Flop</title>
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<p>
This circuit is a
<a href="http://en.wikipedia.org/wiki/Flip-flop_%28electronics%29#Edge-triggered_D_flip-flop"
>edge-triggered D flip-flop</a>. It functions the same as a
<a href="e-masterslaveff.html">master-slave flip-flop</a> (except that it is positive-edge
triggered), but uses fewer gates in its design.
<p>
The circuit consists of 3 <a href="e-nandff.html">set-reset latches</a>. The latch on the right
controls the output. When the D input (at lower left) is high, the lower-left latch is set
whenever the clock is low. This triggers the set input of the upper-left latch, which
sets the output latch whenever the clock is high.
When the D input is low, the lower-left latch is reset, causing the output latch to be
reset whenever the clock is high.
<p>
The result is that output can only change state when the clock makes a transition from low to high.
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Next: <a href="e-jkff.html">JK Flip-Flop</a><p>
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<br>Generated Wed Dec 7 2016
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